A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25μ BiCMOS Technology

Author

Sarkar, Surajit ; Ghosh, Arindrajit ; Banerj, Swapna

Author_Institution

QualCore Logic Ltd., Hyderabad

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

A fully differential low power 10-bit 200MSPS sample and hold has been designed for the front-end of a pipelined analog-to-digital converter using 0.25μm BiCMOS technology. Switched capacitor differential topology has been used with special care taken in linearization of switches. The key issues of the design are optimization of speed, accuracy and power minimization. An op-amp (OTA) having very fast settling time of 1.67ns is designed to meet the speed requirement of the sample and hold. The sample and hold consumes 11mW power while occupying an area of 0.07 mm² including clock driver circuitry. Analog and digital power-supplies used are 3V and 2.5V respectively

Keywords

BiCMOS analogue integrated circuits; analogue-digital conversion; linearisation techniques; low-power electronics; operational amplifiers; sample and hold circuits; switched capacitor networks; 0.25 micron; 1.67 ns; 10 bit; 11 mW; 2.5 V; 3 V; BiCMOS technology; OTA; clock driver circuitry; fully differential sample and hold circuit; low power sample and hold circuit; pipelined analog-to-digital converter; switched capacitor; Analog-digital conversion; BiCMOS integrated circuits; Capacitors; Clocks; Design optimization; Driver circuits; Minimization; Operational amplifiers; Switches; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342248

Filename

4145317