Title :
Test point insertion: scan paths through combinational logic
Author :
Lin, Chih Chang ; Sadowska, Malgorzata Marek ; Cheng, Kwang Ting ; Lee, Mike Tien Chien
Author_Institution :
Mentor Graphics Corp., San Jose, CA, USA
Abstract :
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses the existing functional logic; as a result, the design-for-testability (DFT) overhead on area or timing can be minimized. In this paper we show an algorithm which considers the test point insertion for reducing the area overhead for the full scan design. We also discuss its application to timing-driven partial scan design
Keywords :
circuit CAD; combinational circuits; design for testability; integrated circuit design; logic CAD; logic testing; combinational logic; design-for-testability; functional logic; low-overhead scan design methodology; scan paths; test point insertion; timing-driven partial scan design; Automatic test pattern generation; Circuit testing; Controllability; Design for testability; Design methodology; Flip-flops; Logic design; Logic testing; Multiplexing; Permission;
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-3294-6
DOI :
10.1109/DAC.1996.545585
