Title :
A 65 V, 0.56 mΩ.cm2 Resurf LDMOS in a 0.35 μm CMOS process
Author :
Zhu, R. ; Parthasarathy, V. ; Bose, A. ; Baird, R. ; Khemka, V. ; Roggenbauer, T. ; Collins, D. ; Chang, S. ; Hui, P. ; Ger, M.L. ; Zunino, M.
Author_Institution :
Semicond. Products Sector, Motorola Inc., Mesa, AZ, USA
Abstract :
This paper reports a 65 V, 0.56 mΩ.cm2 Resurf LDMOS with a wide safe operating area integrated into a 0.35 μm CMOS process. The superior performance of the device is achieved by advanced implantation techniques without additional thermal steps and without resorting to high-tilt implants
Keywords :
CMOS integrated circuits; ion implantation; power integrated circuits; 0.35 micron; 65 V; CMOS process integration; Resurf LDMOS power device; ion implantation; safe operating area; Breakdown voltage; CMOS process; CMOS technology; Doping profiles; Implants; Logic devices; Optimized production technology; Oxidation; Silicon; Voltage control;
Conference_Titel :
Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on
Conference_Location :
Toulouse
Print_ISBN :
0-7803-6269-1
DOI :
10.1109/ISPSD.2000.856838
