A parallel precorrected FFT based capacitance extraction program for signal integrity analysis

Author

Aluru, N.R. ; Nadkarni, V.B. ; White, J.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

fYear

1996

fDate

3-7 Jun, 1996

Firstpage

363

Lastpage

366

Abstract

In order to optimize interconnect to avoid signal integrity problems, very fast and accurate 3-D capacitance extraction is essential. Fast algorithms, such as the multipole or precorrected Fast Fourier Transform (FFT) accelerated methods in programs like FASTCAP, must be combined with techniques to exploit the emerging cluster-of-workstation based parallel computers like the IBM SP2. In this paper, we examine parallelizing the precorrected FFT algorithm for 3-D capacitance extraction and present several algorithms for balancing workload and reducing communication time. Results from a prototype implementation on an eight processor IBM SP2 are presented for several test examples, and the largest of these examples achieves nearly linear parallel speed-up

Keywords

capacitance; circuit analysis computing; digital simulation; fast Fourier transforms; integrated circuit modelling; parallel algorithms; IBM SP2; communication time; distributed parallelism; fast Fourier transform; high performance integrated circuits; integrated circuit packaging; linear parallel speed-up; parallel precorrected FFT based capacitance extraction program; signal integrity analysis; Acceleration; Capacitance; Clustering algorithms; Concurrent computing; Conductors; Contracts; Permission; Signal analysis; Signal design; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference Proceedings 1996, 33rd

Conference_Location

Las Vegas, NV

ISSN

0738-100X

Print_ISBN

0-7803-3294-6

Type

conf

DOI

10.1109/DAC.1996.545602

Filename

545602