DocumentCode :
2239889
Title :
Accelerated fault simulation by propagating disjoint fault-sets
Author :
Teshima, Shigeharu ; Chujo, Norio ; Sano, N. ; Nagase, Hirokazu ; Takigawa, M.
Author_Institution :
Toyota Central Res. & Dev. Lab. Inc., Aichi, Japan
fYear :
1988
fDate :
27-30 June 1988
Firstpage :
116
Lastpage :
121
Abstract :
The authors propose a novel fault simulation method (the compressive method), which extends the idea of fault propagation on which the deductive and concurrent method are based. A fault set is used as a unit of fault propagation; it is a set of faults which cause the same effect on the primary outputs for a given input pattern. Thus, faults in the set are propagated in a lump, just like an individual fault in the concurrent method, and fault propagation is accelerated in proportion to number of elements in a fault set. The compressive method introduces union operation on the fault sets. The operation dynamically gathers faults into a fault set so that they are propagated in a bit unit. Fault simulation using this method provides better performance than the concurrent method; simulation time is shortened by 50-83% and memory storage is reduced by 50-80% in simulating a combinational circuit.<>
Keywords :
integrated circuit testing; integrated logic circuits; logic testing; combinational circuit; compressive method; concurrent method; disjoint fault-sets; fault propagation; fault simulation; Acceleration; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Computer architecture; Electrical fault detection; Fault detection; Large-scale systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1988. FTCS-18, Digest of Papers., Eighteenth International Symposium on
Conference_Location :
Tokyo, Japan
Print_ISBN :
0-8186-0867-6
Type :
conf
DOI :
10.1109/FTCS.1988.5308
Filename :
5308
Link To Document :
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