DocumentCode :
2239994
Title :
Functional verification methodology of Chameleon processor
Author :
Benjamin, M.
fYear :
1996
fDate :
3-7 Jun, 1996
Firstpage :
421
Lastpage :
426
Abstract :
Functional verification of the new generation microprocessor developed by SGS-Thomson Microelectronics makes extensive use of advanced technologies. This paper presents a global overview of the methodology and focuses on three main aspects: Use of acceleration and emulation technologies for the verification of the VRDL specification in the early stages of the design; development and use of sequential verification methods built upon a commercially available formal proof tool; and extensive use of combinational proof for circuit-level verification, in conjunction with transistor abstraction
Keywords :
formal verification; hardware description languages; logic CAD; logic testing; microprocessor chips; Chameleon processor; SGS-Thomson Microelectronics; VRDL specification; acceleration; circuit-level verification; combinational proof; emulation; formal proof tool; functional verification; new generation microprocessor; sequential verification; transistor abstraction; Acceleration; Circuit simulation; Computer architecture; Emulation; Microelectronics; Microprocessors; Permission; Process design; Silicon; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
ISSN :
0738-100X
Print_ISBN :
0-7803-3294-6
Type :
conf
DOI :
10.1109/DAC.1996.545613
Filename :
545613
Link To Document :
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