DocumentCode
2240089
Title
Low power pipelined radix-2 FFT processor for speech recognition
Author
Wu, Gin-Der ; Lei, Ying
Author_Institution
Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli
fYear
2006
fDate
24-26 April 2006
Abstract
It is important to develop a high-performance FFT/IFFT processor to meet the requirements of real-time, low area (low cast), and low power in different applications. In this paper, we proposed a radix-2 pipeline FFT processor for Mel frequency cepstral coefficient (MFCC). This novel architecture can reduce more power consumption. This approach is very attractive for MFCC speech feature extraction
Keywords
cepstral analysis; digital signal processing chips; fast Fourier transforms; feature extraction; pipeline processing; speech recognition; MFCC speech feature extraction; Mel frequency cepstral coefficient; high-performance IFFT processor; low power pipelined radix-2 FFT processor; power consumption; speech recognition; Asynchronous circuits; Clocks; Computer architecture; Delay; Energy consumption; Hardware; Mel frequency cepstral coefficient; Memory architecture; Pipelines; Speech recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
System of Systems Engineering, 2006 IEEE/SMC International Conference on
Conference_Location
Los Angeles, CA
Print_ISBN
1-4244-0188-7
Type
conf
DOI
10.1109/SYSOSE.2006.1652312
Filename
1652312
Link To Document