DocumentCode
2240160
Title
A fast state reduction algorithm for incompletely specified finite state machines
Author
Higuchi, Hiroyuki ; Matsunaga, Yusuke
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
1996
fDate
3-7 Jun, 1996
Firstpage
463
Lastpage
466
Abstract
This paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a BDD. Experimental results are given to demonstrate that the algorithm described here is faster and obtains better solutions than conventional methods
Keywords
computational complexity; finite state machines; logic design; BDD; compatibles; fast state reduction; finite state machines; iterative improvements; state reduction; Automata; Binary decision diagrams; Data structures; Heuristic algorithms; Iterative algorithms; Laboratories; Logic; Performance evaluation; Permission; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference Proceedings 1996, 33rd
Conference_Location
Las Vegas, NV
ISSN
0738-100X
Print_ISBN
0-7803-3294-6
Type
conf
DOI
10.1109/DAC.1996.545620
Filename
545620
Link To Document