Title :
High aspect ratio quarter-micron electroless copper integrated technology
Author :
Shacham-Diamand, Y. ; Lopatin, S.Y.
Author_Institution :
Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
Abstract :
In this paper, we present recent results of electroless Cu line and CoWP barrier/protection layer depositions with emphasis on copper encapsulation at low temperature for on-chip wiring of very high aspect ratio. We present a profile study of barrier/seed layers covered with thin (/spl sim/100 nm) electroless Cu films by SEM cross sections and step coverage in trenches and vias as a function of aspect ratio.
Keywords :
coating techniques; copper; diffusion barriers; electroless deposition; encapsulation; integrated circuit metallisation; scanning electron microscopy; 0.25 micron; CoWP; CoWP barrier layer; Cu; Cu line; SEM cross section; aspect ratio; electroless deposition; integrated circuit technology; low temperature encapsulation; on-chip wiring; protection layer; seed layer; step coverage; thin film; trench; via; Chemical technology; Chemical vapor deposition; Conductivity; Copper; Metallization; Protection; Temperature; Tin; Transistors; Ultra large scale integration;
Conference_Titel :
Materials for Advanced Metallization, 1997. MAM '97 Abstracts Booklet., European Workshop
Conference_Location :
Villard de Lans, France
DOI :
10.1109/MAM.1997.621041
