Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding

Author

Chao, Yi-Chih ; Wei, Shih-Tse ; Yang, Jar-Ferr ; Liu, Bin-Da

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

259

Lastpage

262

Abstract

This paper proposes an efficient architecture, which combines the context-based adaptive variable length coding (CAVLC) decoder and inverse quantization (IQ) together to simplify the H.264/AVC decoder. The IQ function is effectively moved to the run before stage in the CAVLC decoder. With this efficient arrangement, it can easily implement the interface between CAVLC decoder and IQ without additional logic circuit. However, the authors also use pipeline skill to improve the performance. Because there are data dependency properties in the CAVLC decoder, it should modify the algorithm in the standard to realize the pipeline skill. The authors implement this architecture with UMC 0.18 mum cell library. The simulation results show the operation frequency can achieve 200 MHz. The total number of logic gate counts is 9.23k. For the real-time requirement, it achieves 1080HD (1920times1088) @30 frames/sec while the clock frequency is set to 195 MHz

Keywords

adaptive codes; logic gates; variable length codes; video coding; 0.18 micron; 195 MHz; 200 MHz; H.264/AVC decoding; UMC; cell library; combined CAVLC decoder; context-based adaptive variable length coding; inverse quantization; logic gate; Automatic voltage control; Circuit simulation; Clocks; Decoding; Frequency; Libraries; Logic circuits; Logic gates; Pipelines; Quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342381

Filename

4145380