• DocumentCode
    2241088
  • Title

    Pareto based Multi-objective Mapping IP Cores onto NoC Architectures

  • Author

    Zhou, Wenbiao ; Zhang, XYan ; Mao, Zhigang

  • Author_Institution
    Shenzhen Graduate Sch., Harbin Inst. of Technol., Shenzhen
  • fYear
    2006
  • fDate
    4-7 Dec. 2006
  • Firstpage
    331
  • Lastpage
    334
  • Abstract
    This paper presents a multi-objective exploration approach to map the IP cores onto the network on chip (NoC). The NoC mapping problem is treated as a two conflicting objective optimization problem of minimizing the average hop and achieving the thermal balance. Thus a set of Pareto-optimal mapping, instead of a single mapping, is an efficient solution. The proposed approach uses a novel representation and the multi-objective genetic algorithm capable of finding multiple Pareto-optimal solutions simultaneously for different performance requirement. Experimental results show the approach is highly efficient and accurate
  • Keywords
    IP networks; Pareto optimisation; genetic algorithms; network-on-chip; IP cores; Pareto-optimal mapping; genetic algorithms; multi-objective mapping; network-on-chip; Circuits; Costs; Encoding; Energy consumption; Genetic algorithms; Minimization; Network-on-a-chip; Region 5; Sorting; Low Power; Mapping; NoC; Thermal;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
  • Conference_Location
    Singapore
  • Print_ISBN
    1-4244-0387-1
  • Type

    conf

  • DOI
    10.1109/APCCAS.2006.342418
  • Filename
    4145398