Single channel digital tanlock based loop

This paper presents a novel design of a digital phase lock loop based on the digital tanlock loop (DTL) architecture. The new simplified design eliminates the requirement for a delay block. Instead, it incorporates an adaptation mechanism whose output feeds into the phase detector block of the new design and controls the acquisition time and locking range of the loop. The new proposed loop design was thoroughly tested and the results indicate that its overall performance compares favourably with that of the conventional time delay digital tanlock loop (TDTL).