Arithmetic implementation techniques and methodologies for 3G uplink reception in Xilinx FPGAs

DSP system-level design decisions can have significant effects on field programmable gate array (FPGA) hardware cost and efficiency. In this paper we demonstrate how modifying filter coefficients and taking advantage of non-canonical implementation techniques can yield reduced FPGA hardware cost. Using the root-raised cosine (RRC) pulse shaping filters required in the 3G uplink reception chain as an example, different implementation techniques are compared in terms of DSP system performance and FPGA cost. RRC filter performance is evaluated through simulation of the adjacent channel selectivity (ACS) test. Simulation results are presented and the differing hardware structures are evaluated.