DocumentCode :
2241174
Title :
A 6-bit 2.704Gsps DAC for DS-CDMA UWB
Author :
Jung, Jae-Jin ; Park, Bong-Hyuck ; Choi, Sang-Seong ; Lim, Shin-Il ; Kim, Suki
Author_Institution :
Korea Univ., Seoul
fYear :
2006
fDate :
4-7 Dec. 2006
Firstpage :
347
Lastpage :
350
Abstract :
This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13mum CMOS technology shows s spurious free dynamic range (SFDR) of 41dB at f signal 300Mhz. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of 0.76mm2
Keywords :
CMOS integrated circuits; code division multiple access; digital-analogue conversion; spread spectrum communication; transceivers; ultra wideband communication; 0.13 micron; CMOS technology; DAC; DS-CDMA; UWB transceivers; deglitch; differential nonlinearity; integral nonlinearity; spurious free dynamic range; CMOS technology; Circuits; Decoding; Dynamic range; Multiaccess communication; Sampling methods; Semiconductor device measurement; Signal resolution; Switches; Transceivers; CMOS; DAC; Deglitch; UWB;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
Type :
conf
DOI :
10.1109/APCCAS.2006.342441
Filename :
4145402
Link To Document :
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