A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter

This work proposes a 14b 100MS/s 0.18mum CMOS ADC for the fourth-generation mobile communication systems. The proposed 3-stage pipeline ADC, whose architecture is verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b sub-ranging flash ADC based on open-loop offset sampling and interpolation to obtain a small chip area at 6b. The prototype ADC implemented in a 0.18mum CMOS technology demonstrates the measured DNL and INL within 1.03LSB and 5.47LSB, respectively, while the ADC shows an SNDR of 59dB and an SFDR of 72dB with an active die area of 3.4mm² and a power consumption of 145mW at 100MS/s and 1.8V