An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN

Author

Ha, Seong-Min ; Nam, Tae-Kyu ; Yoon, Kwang S.

Author_Institution

Sch. of EE, Inha Univ.

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

355

Lastpage

358

Abstract

This paper describes an I/Q channel 12bit 120MS/s digital-to-analog converter (DAC) for WLAN application. The proposed DAC implemented in 0.35mum CMOS n-well process employs three stage 4 bit thermometer decoders to minimize glitch energy and linearity error. The measurement results show a plusmn1.6LSB/plusmn1.3LSB of INL/DNL and 31 pVmiddots of glitch energy. ENOB and SFDR are measured to be 10.5bit and 71.09dB @ Fs = 120MHz and Fin = 1MHz with a total power consumption of 105mW

Keywords

CMOS integrated circuits; codecs; digital-analogue conversion; thermometers; wireless LAN; 0.35 micron; 1 MHz; 105 mW; 12 bit; 120 MHz; 4 bit; CMOS n-well process; I/Q channel CMOS DAC; WLAN application; digital-to-analog converter; glitch energy; linearity error; three stage thermometer decoders; wireless local area network; CMOS process; Decoding; Energy resolution; Latches; Linearity; Mirrors; Signal design; Signal processing; Transceivers; Wireless LAN; CMOS; DAC; Thermometer decoder; WLAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342443

Filename

4145404

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2241218