A 0.18-μm CMOS UWB Low Noise Amplifier for Full-Band (3.1-10.6GHz) Application

The paper presents the design of a band group 1~5 UWB low noise amplifier in the range between 3.1 to 10.6GHz. The circuit consists of a two-stage topology to implement a low noise amplifier based on the TSMC 0.18-mum RF CMOS process. The first stage is the folded cascode configuration that is used to attain low-power dissipation and low supply voltage. Negative feedback is adopted to enhance the bandwidth of the first stage. In order to achieve simultaneously a high gain and ultra-wide bandwidth, the addition of a common-source stage behind the folded cascode circuit provides extra gain and gain flatness. A RLC shunt-shunt feedback is used to attain the broadband gain requirement of the second stage. The simulated results show the better performances of S21 above 12dB and noise figure below 3.6dB with the 3-dB bandwidth covering from 3.1GHz to 10.6GHz. The first-stage circuit of LNA drains 22mA from a 0.9V supply and the second-stage circuit of LNA drains 8mA from a 0.85V supply voltage. The total circuit consumes a very low power of 27mW. The chip area is 1.195mm×1.275 mm