Title :
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC
Author :
Ching-Lung Su ; Wei-Sen Yang ; Ya-Li Chen ; Yang, Wei-Sen ; Chen, Ya-Li ; Guo, Jiun-In ; Tseng, Shau-Yin
Author_Institution :
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Yun-Lin
Abstract :
In this paper, a low complexity high quality motion estimation architecture design was proposed for MPEG-4 AVC/H.264 video coding applications. The proposed design is based on a low complexity algorithm that reduces over 90% of complexity at the cost of 0.06968dB and 0.08296dB PSNR drop as compared to JM9.3 full search with a plusmn32 search range at CIF and D1 formats, respectively. Besides, the algorithm provides a capacity of scalable search range. We have also exploited an on-chip memory rotation scheme and a configurable summation of absolute difference processor to reduce the on-chip memory bandwidth and the hardware cost. According to the TSMC 0.18mum CMOS technology, the proposed design costs 47.9K gates, 4K bits of Cur./Ref. pixel buffer and 22 Kbits SRAM with the maximum working frequency of 125MHz. The proposed design can achieve realtime motion estimation on D1 video and HD720 video when operating at 40MHz and 105MHz, respectively
Keywords :
CMOS integrated circuits; SRAM chips; buffer circuits; motion estimation; real-time systems; video coding; 0.18 micron; 105 MHz; 125 MHz; 22 kbit; 40 MHz; CIF format; CMOS technology; D1 format; D1 video; HD720 video; MPEG-4 AVC/H.264 video coding; SRAM; buffer; motion estimation architecture design; on-chip memory bandwidth; on-chip memory rotation scheme; processor; realtime motion estimation; Algorithm design and analysis; Automatic voltage control; Bandwidth; CMOS technology; Costs; Hardware; MPEG 4 Standard; Motion estimation; PSNR; Video coding;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342454
