Embedded Genesio-Tesi chaotic generator for ciphering communications

In this paper, we propose a hardware implementation to conceiver an embedded chaotic key generator based on the Genesio-Tesi system for designing a real-time secure symmetric encryption scheme. This proposed architecture is particularly attractive since it provides a low cost data encryption for securing communications of embedded systems while still providing a good trade-off between performance and hardware resources. Our experimental results have demonstrated the feasibility and the efficiency in terms of throughput and resources cost required on Xilinx FPGA Virtex II technology.