Soft-Error Hardening Designs of Nanoscale CMOS Latches

As technology scales down in the deep sub-micron/nano ranges, CMOS circuits are more sensitive to externally induced phenomena to likely cause the occurrence of so-called soft errors. Therefore, the operation of these circuits to tolerate soft errors is a strict requirement in todaypsilas designs. Traditional error tolerant methods result in significant cost penalties in terms of power, area and performance, and the development of low-cost hardened designs for storage cells (such as latches and memories) is of increasing importance. This paper proposes new hardened designs for CMOS latches at 32 nm feature size. Three hardened latch circuits are proposed; two of these circuits are Schmitt trigger based, while the third one utilizes a cascode configuration in the feedback loop. These new hardened latches are shown to have superior performance in terms of power-delay product as well as highest tolerance to soft errors (measured by the critical charge) than existing hardened latches. Extensive simulation results are provided using the predictive technology file for 32 nm feature size in CMOS.