Title :
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric
Author :
Wang, Zheng ; Walker, D.M.H.
Author_Institution :
Dept. of Comput. Sci. & Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector count on ISCAS89 and industry designs.
Keywords :
automatic test pattern generation; circuit testing; delay circuits; fault diagnosis; CodGen ATPG tool; ISCAS89; compact delay test generation; global delay faults; high fault coverage; industry design; local delay faults; realistic low cost fault coverage metric; test generation time reduction; Automatic test pattern generation; Circuit faults; Circuit testing; Computer science; Costs; Delay effects; Electrical fault detection; Fault detection; Manufacturing industries; Very large scale integration; ATPG; delay test; fault coverage metric;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.55
