VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT

In this paper, we propose a pipeline architecture for VLSI implementation of multilevel lifting-based discrete wavelet transform (DWT). The proposed architecture can compute multilevel lifting DWT of an TV-point data-sequence in N/2 clock cycles. For implementing the TV -point DWT using (5, 3) filters the proposed structure requires two more multipliers and four more adders compared with the corresponding existing structure, but it provides twice the throughput and requires less than half the number of registers and shifters compared with those of the other. Apart from that, when faster implementation is not required, the proposed architecture may be used for low-power implementations of multilevel lifting DWT