DocumentCode :
2241892
Title :
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions
Author :
Flanigan, E. ; Tragoudas, S. ; Abdulrahman, A.
Author_Institution :
Dept. of ECE, Southern Illinois Univ., Carbondale, IL, USA
fYear :
2009
fDate :
3-7 May 2009
Firstpage :
140
Lastpage :
145
Abstract :
A recent decision diagram-based algorithm was able to generate test patterns for each sensitizable path delay fault. Although scalable this approach results to prohibitively long test sets. This paper presents a novel technique to intelligently select paths for compaction. It guarantees optimal compaction subject to the order of processing faults. The compaction rate is superior to any published method, even for the small benchmarks where enumerative compaction methods have been proposed. Experimental results on the publicly available benchmarks demonstrate the scalability of the proposed method.
Keywords :
automatic test pattern generation; compaction; decision diagrams; delay circuits; decision diagram based algorithm; optimal compaction; path delay faults; processing faults; publicly available benchmarks; scalable compact test pattern generation; small benchmarks; Automatic test pattern generation; Benchmark testing; Boolean functions; Circuit faults; Circuit testing; Compaction; Data structures; Delay; Robustness; Test pattern generators; PDF; compaction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
ISSN :
1093-0167
Print_ISBN :
978-0-7695-3598-2
Type :
conf
DOI :
10.1109/VTS.2009.22
Filename :
5116624
Link To Document :
بازگشت