Understanding Power Supply Droop during At-Speed Scan Testing

The paper explores the effects of power-supply droop during scan based at-speed test application. The unnatural supply voltage profile that results when the capture clocks are fired during such tests can lead to artificial failures and bring into question the validity of using structural at-speed testing as a delay defect screen. The experiments described in this paper attempt to fully characterize this effect in a number of different ways. Although the focus of this publication is mainly transition scan patterns, the results are equally applicable to path-delay scan testing.