Title :
Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering
Author :
Velamati, Naveen ; Daasch, Robert
Author_Institution :
Integrated Circuits Design & Test Lab., Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
Abstract :
In this paper an analytical extension to the ITRS multi-site efficiency model is proposed to obtain the distribution of multi-site efficiency. Multi-site testing is becoming one of the most popular ways for test time reduction, increasing the test throughput and reducing the overall test cost. In the model, the efficiency of multi-site testing is computed from process parameters (e.g. yield, yield clustering at wafer sort), test program parameters parallel and serial test times, and multi-site count. Multi-site trade-offs and benefits to average test time are evaluated by Monte-Carlo simulations.
Keywords :
Monte Carlo methods; VLSI; integrated circuit modelling; integrated circuit testing; integrated circuit yield; Monte-Carlo simulations; multi-site efficiency; multi-site testing; parallel to serial test times; test cost reduction; Analytical models; Automatic testing; Circuit analysis computing; Circuit testing; Concurrent computing; Costs; Integrated circuit synthesis; Integrated circuit testing; Laboratories; Sequential analysis; Average test time; Multi-site testing; Test cost reduction; Test time reduction; Yield ramp;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.42
