Title :
Low power conditional sum adder using pass logic topology
Author :
Saleem, Dhia ; Al-Khalili, Dhamin
Author_Institution :
Nortel Semicond., Nepean, Ont., Canada
Abstract :
The Low Power Conditional Sum Adder (CSA) has been analyzed using various logic styles. Pass logic topology implementation offered low power delay product and occupied less silicon area compared to other topologies. A test chip for two versions of the CSA using pass logic and standard CMOS has been designed and fabricated using 0.5 μ CMOS technology. Test results indicate that 50% power saving has been achieved in Pass Logic CSA
Keywords :
CMOS logic circuits; adders; formal logic; microprocessor chips; CMOS technology; Pass Logic CSA; logic styles; low power conditional sum adder; low power delay product; pass logic topology; pass logic topology implementation; standard CMOS; test chip; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit topology; DH-HEMTs; Logic design; Logic devices; Logic testing;
Conference_Titel :
Electrical and Computer Engineering, 1998. IEEE Canadian Conference on
Conference_Location :
Waterloo, Ont.
Print_ISBN :
0-7803-4314-X
DOI :
10.1109/CCECE.1998.682537
