Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC

Modern mixed-signal/RF circuits with digital calibration capabilities could achieve significant performance improvements once the calibration process is completed; however, the calibration time is often very long - in the order of hundreds of milliseconds or even seconds. As testing such devices would require completion of calibration first, lengthy calibration time would result in unacceptably long testing time. In this paper, we propose design-for-testability modifications and acceleration techniques for adaption algorithms to reduce the calibration time required for testing a digitally-calibrated pipelined ADC. For the pipelined ADC proposed in, simulation results show that the proposed techniques can achieve a 60X reduction in the calibration time.