Advanced/3D packaging and materials integrity: Stress-induced effects and mechanical properties of new ultra low-k dielectrics for on-chip interconnect stacks

The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development [1]. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies [2]. It requires the determination of materials properties, including Young´s modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. Particularly for sub-m structures, materials properties change depending on the size of the structure. For some materials, especially the materials used in packaging, these characteristics are a non-linear function of temperature, i. e. temperature-dependent materials data have to be determined [3]. For polycrystalline materials, their microstructure has to be considered.