Title :
High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video Coding
Author :
Tsai, Min-Chi ; Chang, Tian-Sheuan
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
Abstract :
This paper presents a high-performance VLSI architecture for context adaptive variable length coding (CAVLC) used in the MPEG-4 AVC/H.264 video coding. Instead of only the coarse-grained 8times8 zero block skipping in the previous design, the proposed design implements the fine-grained zero skipping at the 4times4 block level and the individual coefficient level. The implementation with 0.18mum CMOS process just needs average 6.88 cycles for one block coding and costs 11.9K gates when working at 100 MHz. This design saves more than half of cycle count and 48% of area cost when compared with the other designs
Keywords :
CMOS integrated circuits; VLSI; encoding; video coding; 0.18 micron; 100 MHz; AVC/H.264; CMOS process; MPEG-4; VLSI architecture; context adaptive variable length coding encoder; video coding; Automatic voltage control; Block codes; CMOS process; Code standards; Costs; Encoding; MPEG 4 Standard; Statistics; Very large scale integration; Video coding;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342056
