Title :
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU
Author :
Manikandan, P. ; Liu, B.-D. ; Chiou, L.Y. ; Sundar, G. ; Mandal, C.R.
Author_Institution :
Dept. of Electr. Eng., National Cheng Kung Univ., Tainan
Abstract :
The paper presents a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay
Keywords :
CMOS logic circuits; asynchronous circuits; low-power electronics; CMOS domino logic; asynchronous ALU; asynchronous design; delay insensitive; dual rail four-phase logic; low power ALU; low power consumption; Clocks; Delay; Design methodology; Energy consumption; Latches; Logic design; Pipelines; Protocols; Rails; Timing;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342057
