DocumentCode
2242629
Title
Power analysis for sequential circuits at logic level
Author
Schneider, Peter H. ; Senn, Matthias A. ; Wurth, Bernd
Author_Institution
Siemens AG, Munich, Germany
fYear
1996
fDate
16-20 Sep 1996
Firstpage
22
Lastpage
27
Abstract
This paper introduces a novel technique to determine the transition probabilities of internal signals for sequential circuits. We account for temporal correlations of primary inputs and internal signals, sequential correlations, and spatial correlations of internal signals. For this purpose, we exploit and combine concepts of unrolling reconvergence analysis, decomposing packers of temporally correlated variables, and Markov chains. Experimental results demonstrate the high accuracy and efficiency of our technique
Keywords
CMOS logic circuits; Markov processes; circuit analysis computing; logic CAD; logic testing; sequential circuits; Markov chains; decomposing packers; internal signals; primary inputs; sequential circuits; sequential correlations; spatial correlations; temporal correlations; temporally correlated variables; transition probabilities; unrolling reconvergence analysis; Circuit analysis; Circuit simulation; Computational modeling; Counting circuits; Logic circuits; Monte Carlo methods; Nonlinear equations; Sequential circuits; Switches; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location
Geneva
Print_ISBN
0-8186-7573-X
Type
conf
DOI
10.1109/EURDAC.1996.558047
Filename
558047
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