A fully parallel VLSI implementation of distributed arithmetic

Author

Li, Weiping ; Burr, James B. ; Peterson, Allen M.

Author_Institution

Lehigh Univ., Bethlehem, PA, USA

fYear

1988

fDate

7-9 June 1988

Firstpage

1511

Abstract

A novel architecture to implement distributed arithmetic in VLSI is presented. This architecture comprises a serial-in random-out multiport memory and a multi-input adder. The design of a 1.25- mu m CMOS convolution processor chip based on the architecture is reported. Issues in the development of chip architecture and design tools are discussed.<>

Keywords

CMOS integrated circuits; VLSI; computerised signal processing; digital arithmetic; digital signal processing chips; integrated logic circuits; parallel architectures; 1.25 micron; CMOS convolution processor chip; DSP; design tools; distributed arithmetic; fully parallel VLSI implementation; logic circuits; multi-input adder; serial-in random-out multiport memory; signal processing; Arithmetic; CMOS process; Clocks; Computer architecture; Distributed computing; Hardware; Read only memory; Shift registers; Very large scale integration; Zinc;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15217

Filename

15217

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2242640