DocumentCode
2242675
Title
Low Power Multiplier with Bypassing and Tree Strucuture
Author
Kuo, Ko-Chi ; Chou, Chi-Wen
Author_Institution
Dept. of Comput. Sci. & Eng., National Sun Yat-sen Univ., Kaohsiung
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
602
Lastpage
605
Abstract
In this paper, a new design technique for low power multiplier is introduced. This technique utilizes the bypassing method to minimize the switching activities and tree structure decrease the critical path. The design of circuit uses the standard TSMC 0.18mum technology. According to the simulation results, the proposed multiplier design can obtain more power savings than those of counterparts and achieve smaller power-delay product
Keywords
low-power electronics; multiplying circuits; trees (mathematics); 0.18 micron; bypassing method; low power multiplier; power-delay product; standard TSMC; tree structure; Adders; Circuit simulation; Computer science; Design engineering; Digital signal processing; Power dissipation; Power engineering and energy; Switches; Tree data structures; Very large scale integration; bypassing method; low power; multiplier; tree structure;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342060
Filename
4145465
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