Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough?

Author

Piziali, Andrew

fYear

2009

fDate

3-7 May 2009

Firstpage

338

Lastpage

338

Keywords

Computer bugs; Costs; Hardware; Job design; Job shop scheduling; Monitoring; Process design; Testing; Time to market; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2009. VTS '09. 27th IEEE

Conference_Location

Santa Cruz, CA, USA

ISSN

1093-0167

Print_ISBN

978-0-7695-3598-2

Type

DOI

10.1109/VTS.2009.66

Filename

5116658

Link To Document