• DocumentCode
    2242714
  • Title

    A new pipelined digit serial-parallel multiplier

  • Author

    Nibouche, O. ; Bouridane, A. ; Nibouche, M. ; Crookes, D.

  • Author_Institution
    Sch. of Comput. Sci., Queen´´s Univ., Belfast, UK
  • Volume
    1
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    12
  • Abstract
    Digit-serial architectures obtained using traditional unfolding and folding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, a novel approach for the design of pipelined digit serial-parallel multipliers is presented
  • Keywords
    integrated logic circuits; logic design; multiplying circuits; pipeline arithmetic; digit serial-parallel multiplier; multiple pipes architecture; pipelined multiplier; Arithmetic; Design methodology; Digital signal processing; Hardware; Image processing; Pipeline processing; Radar applications; Radar imaging; Radar signal processing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
  • Conference_Location
    Geneva
  • Print_ISBN
    0-7803-5482-6
  • Type

    conf

  • DOI
    10.1109/ISCAS.2000.857013
  • Filename
    857013
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2242714