A pipelined multiply-accumulate unit design for energy recovery DSP systems

Author

Suvakovic, Dusan ; Salama, C. Andre T

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

1

fYear

2000

fDate

2000

Firstpage

16

Abstract

A pipelined 15×15 bit multiply-accumulate (MAC) unit, optimized for energy recovery systems, is presented. The applied architectural and circuit level optimizations are aimed at minimizing the total non-recoverable energy per computation. For that purpose, the number of pipeline stages is minimized, utilizing logic gates based on high fan-in differential NMOS trees. The MAC includes three pipeline stages operated from a two-phase non-overlapping power clock and processes one multiply-accumulate operation per clock cycle. Implemented in 0.25 μm CMOS process and powered from a 1 V power supply, this circuit uses 4.5 pJ of recoverable energy per clock cycle, while dissipating 0.28 pJ of non-recoverable energy

Keywords

CMOS logic circuits; integrated circuit design; logic design; low-power electronics; multiplying circuits; performance evaluation; pipeline arithmetic; signal processing; 0.25 micron; 0.28 pJ; 1 V; 15 bit; 4.5 pJ; CMOS process; MAC datapath design; MAC unit; differential NMOS trees; energy recovery DSP systems; nonoverlapping power clock; performance analysis; pipelined multiply-accumulate unit design; two-phase power clock; CMOS logic circuits; CMOS process; Capacitance; Clocks; Digital signal processing; Energy consumption; Latches; Logic gates; MOS devices; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857014

Filename

857014