Title :
Methods for on-chip embedding of path delay test vectors
Author :
Kagaris, U. ; Tragoudas, S.
Author_Institution :
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
We propose two methods for embedding on-chip a given set of pairs of test patterns that have been generated by an arbitrary ATPG tool for path delay faults. The first method uses an LFSR with multiplexers. It applies to any set of test patterns and it is experimentally verified to have reasonable hardware overhead. The second method applies to the important special case of single input pattern changes within each pair and is very hardware overhead efficient
Keywords :
VLSI; automatic test pattern generation; delays; digital integrated circuits; integrated circuit testing; logic testing; shift registers; ATPG tool; LFSR; hardware overhead efficient method; multiplexers; onchip embedding; path delay faults; path delay test vectors; single input pattern changes; test patterns; Bonding; Circuit faults; Circuit testing; Delay effects; Ducts; Electrical fault detection; Fault detection; Hardware; Propagation delay; Test pattern generators;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857032
