Title :
A partial scan design by unifying structural analysis and testabilities
Author :
Park, J. ; Shin, S. ; Park, S.
Author_Institution :
Appeal Telecom, South Korea
Abstract :
To overcome the large extra hardware overhead attendant in the full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. In this paper we analyzed and unified the strength of the techniques by structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flops but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for the most ISCAS89 benchmark circuits
Keywords :
design for testability; flip-flops; integrated circuit design; integrated circuit testing; logic design; logic testing; ISCAS89 benchmark circuits; high fault coverage; partial scan design; structural analysis; testabilities; Circuit faults; Circuit testing; Controllability; Electronic equipment testing; Feedback; Flip-flops; Hardware; Observability; Sequential analysis; Sequential circuits;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857033
