A partial scan design by unifying structural analysis and testabilities

To overcome the large extra hardware overhead attendant in the full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. In this paper we analyzed and unified the strength of the techniques by structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flops but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for the most ISCAS89 benchmark circuits