DocumentCode :
2243564
Title :
High performance BDD package by exploiting memory hierarchy
Author :
Sanghavi, Jagesh V. ; Ranjan, Rajeev K. ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear :
1996
fDate :
3-7 Jun, 1996
Firstpage :
635
Lastpage :
640
Abstract :
The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using an iterative breadth-first technique directed towards localizing the memory accesses to exploit the memory system hierarchy. The new memory-oriented performance features of this package are: 1) an architecture independent customized memory management scheme, 2) the ability to issue multiple independent BDD operations (superscalarity), and 3) the ability to perform multiple BDD operations even when the operands of some BDD operations are the result of some other operations yet to be completed (pipelining). A comprehensive set of BDD manipulation algorithms are implemented using the above techniques. Unlike the breadth-first algorithms presented in the literature, the new package is faster than the state-of-the-art BDD package by a factor of up to 15, even for the BDD sizes that fit within the main memory. For BDD sizes that do not fit within the main memory, a performance improvement of up to a factor of 100 can be achieved
Keywords :
circuit analysis computing; formal verification; logic CAD; storage management; binary decision diagram based algorithms; customized memory management scheme; depth-first technique; disorderly memory access patterns; high performance package; iterative breadth-first technique; main memory capacity; multiple BDD operations; verification; Availability; Binary decision diagrams; Boolean functions; Data structures; High performance computing; Integrated circuit synthesis; Packaging; Permission; Pipeline processing; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
ISSN :
0738-100X
Print_ISBN :
0-7803-3294-6
Type :
conf
DOI :
10.1109/DAC.1996.545652
Filename :
545652
Link To Document :
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