DocumentCode
2243700
Title
LADPM: Latency-Aware Dual-Partition Multicast Routing for Mesh-Based Network-on-Chips
Author
Li, Jianhua ; Xue, Chun Jason ; Xu, Yinlong
Author_Institution
Dept. of Comput. Sci., City Univ. of Hong Kong, Kowloon, China
fYear
2010
fDate
8-10 Dec. 2010
Firstpage
423
Lastpage
430
Abstract
Networks-on-Chips (NoCs) provides an efficient architectural paradigm as interconnect for state-of-the-art Chip Multi-processors (CMPs). With the increasing development of novel applications in NoCs, one-to-many (multicast) or one-to-all (broadcast) communications are becoming universal and indispensable. The performance constraint metrics, such as power consumption and network latency, are often stringent on NoC systems. Without multicast support, the performance of traditional NoCs will be significantly degraded by such communications. In this paper, we propose Latency-Aware Dual-Partition Multicast (LADPM) routing for mesh-based on-chip networks to reduce packet latency and balance network load. A detailed wormhole router design is also presented for the proposed LADPM scheme. LADPM scheme can adaptively make routing decision based on the distribution of the destination nodes of the multicast traffic. Experimental results, implemented under a cycle-accurate simulator, show that compared with the best known multicast scheme RPM, LADPM reduces Energy-Delay Product by 25.4% on average. More importantly, in heavy traffic load networks, LADPM is a scalable solution.
Keywords
multiprocessing systems; multiprocessor interconnection networks; network routing; network-on-chip; CMP; LADPM; NoC systems; RPM; architectural paradigm; balance network load; broadcast communications; cycle-accurate simulator; destination nodes; energy-delay product; heavy traffic load networks; interconnect; latency-aware dual-partition multicast routing; mesh-based network-on-chips; mesh-based on-chip networks; multicast communication; multicast support; multicast traffic; network latency; one-to-all communication; one-to-many communication; packet latency; performance constraint metrics; power consumption; routing decision; state-of-the-art chip multiprocessors; wormhole router design; Latency-Aware; Load-balance; Multicast; Network-on-Chips (NoCs); Rectilinear Steiner Arborescence;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Systems (ICPADS), 2010 IEEE 16th International Conference on
Conference_Location
Shanghai
ISSN
1521-9097
Print_ISBN
978-1-4244-9727-0
Electronic_ISBN
1521-9097
Type
conf
DOI
10.1109/ICPADS.2010.27
Filename
5695631
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