• DocumentCode
    2243759
  • Title

    State assignment for FSM low power design

  • Author

    Koegst, M. ; Franke, G. ; Feske, K.

  • Author_Institution
    Dept. EAS, FhG IIS Erlangen, Dresden, Germany
  • fYear
    1996
  • fDate
    16-20 Sep 1996
  • Firstpage
    28
  • Lastpage
    33
  • Abstract
    The paper concerns low power design of synchronous FSM and power estimation regarding a given input sequence. A novel and practical approach for state assignment is suggested bp means of which the average rate of register switching is reduced. We achieved more realistic power estimates in comparison with the probabilistic approach. Experimental results demonstrate the effectiveness of the proposed approach
  • Keywords
    circuit optimisation; finite state machines; logic CAD; state assignment; input sequence; low power design; probabilistic approach; register switching; state assignment; Clocks; Frequency; Power dissipation; Signal design; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
  • Conference_Location
    Geneva
  • Print_ISBN
    0-8186-7573-X
  • Type

    conf

  • DOI
    10.1109/EURDAC.1996.558052
  • Filename
    558052
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2243759