Title :
Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits
Author :
Rosdi, Bakhtiar Affendi ; Takahashi, Atsushi
Author_Institution :
Dept. of Commun. & Integrated Syst., Tokyo Inst. of Technol.
Abstract :
A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with a pipelined multiplier verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance
Keywords :
clocks; logic design; multiplying circuits; pipeline processing; scheduling; clock-scheduling; delay balancing; multi-clock cycle paths; pipelined circuits; register replacement; Algorithm design and analysis; Circuit analysis; Clocks; Delay; Integrated circuit technology; Iterative algorithms; Pipeline processing; Registers; Scheduling algorithm; Timing; clock-scheduling; delay balancing; multi-clock cycle paths; pipelined circuits;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342142
