A FPGA pipelining design method of gradient adaptive lattice joint processor

Pipelining technology can improve clock frequency through shortening the critical path of logic device. However, the complex algorithm of gradient adaptive lattice joint processing (GALJP ) results in its lower work clock frequency. A pipeline optimization approach based on the technology of delay leading transfer is proposed. By approximate treatment to the updated weight coefficients and errors in each section of lattice filter and transversal LMS combiner, the critical paths delay of GALJP are reduced greatly. Simulation results show that the work clock frequency of the three-level pipelining filter had increased nearly 30% and it need only additional 60% logic element.