DocumentCode
2244542
Title
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture
Author
Morimoto, Takashi ; Adachi, Hidekazu ; Yamaoka, Kousuke ; Awane, Kazutoshi ; Koide, Tetsushi ; Mattausch, Hans Jürgen
Author_Institution
Res. Center for Nanodevices & Syst., Hiroshima Univ.
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
944
Lastpage
947
Abstract
This paper presents a boundary-scan-only (BSO) video segmentation architecture and its FPGA-based prototype system for 80 times 60 video images (30 fps). In the proposed BSO architecture, an input image is divided into a number of small image blocks. Then only image blocks, that have boundary pixels in the currently grown region, are processed with a block-sized pixel-parallel processing unit. This enables large-sized video segmentation with the compact processing unit, so that FPGA-based real-time video segmentation can be realized. We have developed an evaluation system for 80 times 60 real-time image segmentation with a standard FPGA device in 130 nm CMOS technology, and also evaluated its performance with video images. From this FPGA implementation result, QVGA-sized real-time image segmentation is expected to become possible with a state-of-the-art FPGA device in 90nm CMOS technology
Keywords
boundary scan testing; field programmable gate arrays; image segmentation; large scale integration; 130 nm; 90 nm; CMOS technology; FPGA-based region-growing video segmentation system; QVGA-sized real-time image segmentation; block-sized pixel-parallel processing unit; boundary-scan-only LSI architecture; CMOS technology; Field programmable gate arrays; Image coding; Image processing; Image segmentation; Large scale integration; Pixel; Prototypes; Real time systems; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342217
Filename
4145550
Link To Document