Techniques of Power-gating to Kill Sub-Threshold Leakage

Sub-threshold leakage has increased dramatically with technology scaling, and it already consumes a significant portion of the total power budget in current high-end chip designs. This paper presents a state-of-the-art overview of the power gating techniques that promise to reduce sub-threshold leakage power by up to three orders of magnitude. By emphasizing the challenges and up-to-date solutions, this paper provides an in-depth vision of the current status of power-gating techniques. By analyzing the historic development of power-gating, this paper also outlines possible future evolution courses of the technique