A methodology for validating digital circuits with mutation testing

This paper proposes a systematic methodology for improving functional validation vectors developed to check digital circuits. This method exploits the mutation testing concept originally proposed for software validation. Mutation injects specific functional transformations in circuit descriptions expressed in languages like VHDL or Verilog. These programs, called mutant, are syntactically correct but functionally incorrect. Knowing how these vectors detect functional faults improves the confidence in the design and provide information on the coverage of validation vectors. The paper identifies limits of previous work on mutation testing applied to hardware and proposes method that are better suited to the task