Focused ion beam sample preparation, transmission electron microscopy and electron energy loss spectroscopy analysis of advanced CMOS silicon technology interconnections

Interconnection structures are a major part of modern silicon circuits. For example in the 0.25 /spl mu/m CMOS technology, up to seven metal levels will eventually be used. Moreover, the electrical resistance and capacitance of interconnections are major limiting factors for high speed circuits. For these reasons, great efforts have been made in the semiconductor industry to develop and characterise new metallisation structures. The transmission electron microscopy (TEM) sample preparation technique using focused ion beam (FIB) has recently proven to be a powerful technique for advanced multi-level metallisation circuit analysis. In this paper we develop new improvements in the FIB-TEM preparation technique for accurate positioning and reduced specimen thickness. Samples containing hard material such as tungsten can be thinned to a thickness compatible with the electron energy loss spectroscopy (EELS) technique. Examples of the TEM-EELS chemical analysis of 0.25 /spl mu/m CMOS contacts are shown.