A wave-pipelined CMOS associate router for communication switches

Author

Delgado-Frias, José G. ; Nyathi, Jabulani

Author_Institution

Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

391

Abstract

A wave-pipelining approach is used to improve the performance of a VLSI router. Wave-pipelining has the potential of significantly reducing clock cycle time and silicon real estate. The design approach considered in this paper allows data propagation between stages to occur without the use of intermediate latches. Control signals are designed to ensure that intermixing of data waves does not occur. This study´s results show that using wave-pipelining reduces the clock period. The circuit delays become the limiting factor, preventing further clock cycle time reduction

Keywords

CMOS digital integrated circuits; VLSI; clocks; integrated circuit design; network routing; pipeline processing; telecommunication network routing; telecommunication switching; VLSI router; clock cycle time; clock period; communication switches; data propagation; intermixing; silicon real estate; wave-pipelined CMOS associate router; Circuits; Clocks; Communication switching; Communication system control; Delay effects; Latches; Signal design; Silicon; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857112

Filename

857112