A wave-pipelined CMOS associate router for communication switches

A wave-pipelining approach is used to improve the performance of a VLSI router. Wave-pipelining has the potential of significantly reducing clock cycle time and silicon real estate. The design approach considered in this paper allows data propagation between stages to occur without the use of intermediate latches. Control signals are designed to ensure that intermixing of data waves does not occur. This study´s results show that using wave-pipelining reduces the clock period. The circuit delays become the limiting factor, preventing further clock cycle time reduction