• DocumentCode
    2244975
  • Title

    Electrical Test Conditioning Influence on Total Ionizing Dose Response of SRAMs

  • Author

    Lawrence, Reed K.

  • Author_Institution
    BAE Syst., Manassas, VA, USA
  • fYear
    2012
  • fDate
    16-20 July 2012
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    For CMOS, memory array power up (no pattern loaded) is an acceptable TID worst-case dosing condition; however, this condition may not represent a post exposure worst-case electrical characterization.
  • Keywords
    CMOS integrated circuits; SRAM chips; integrated circuit testing; CMOS; SRAM; electrical test conditioning; memory array power up; total ionizing dose response; worst case dosing condition; worst case electrical characterization; Arrays; Guidelines; Loading; Military standards; Random access memory; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radiation Effects Data Workshop (REDW), 2012 IEEE
  • Conference_Location
    Tucson, AZ
  • ISSN
    2154-0519
  • Print_ISBN
    978-1-4673-2730-5
  • Type

    conf

  • DOI
    10.1109/REDW.2012.6353719
  • Filename
    6353719
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2244975