Title :
Electrical Test Conditioning Influence on Total Ionizing Dose Response of SRAMs
Author :
Lawrence, Reed K.
Author_Institution :
BAE Syst., Manassas, VA, USA
Abstract :
For CMOS, memory array power up (no pattern loaded) is an acceptable TID worst-case dosing condition; however, this condition may not represent a post exposure worst-case electrical characterization.
Keywords :
CMOS integrated circuits; SRAM chips; integrated circuit testing; CMOS; SRAM; electrical test conditioning; memory array power up; total ionizing dose response; worst case dosing condition; worst case electrical characterization; Arrays; Guidelines; Loading; Military standards; Random access memory; Voltage measurement;
Conference_Titel :
Radiation Effects Data Workshop (REDW), 2012 IEEE
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-4673-2730-5
DOI :
10.1109/REDW.2012.6353719
