Title :
A 0.18μm CMOS Receiver with Decision-feedback Equalization for Backplane Applications
Author :
Li, Miao ; Kwasniewski, Tad ; Wang, Shoujun
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont.
Abstract :
Decision-feedback equalization (DFE) is explored to reduce inter-symbol interference (ISI) and crosstalks in highspeed backplane applications. In the design of clock and data recovery (CDR) circuit, embedding DFE within phase and frequency detector (PFD) enhances to recover data inherently from distorted input signals and facilitates to provide DFE with recovered clock. With PRBS15 data signaling at 5-Gb/s over 34" FR4 backplane, SPECTRE simulation in 0.18-μm CMOS process has shown the design feasibility
Keywords :
CMOS integrated circuits; clocks; decision feedback equalisers; intersymbol interference; phase detectors; printed circuits; receivers; synchronisation; 0.18 micron; 34 inches; 5 Gbit/s; CMOS process; CMOS receiver; FR4 backplane; PRBS15 data signaling; SPECTRE simulation; clock and data recovery circuit; decision-feedback equalization; frequency detector; highspeed backplane applications; intersymbol interference; phase detector; Backplanes; Circuits; Clocks; Crosstalk; Decision feedback equalizers; Intersymbol interference; Phase detection; Phase distortion; Phase frequency detector; Signal design;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342266
